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bl blbl bl35p 35p 35p 35p0 00 02 22 2 datasheet datasheet datasheet datasheet 8 88 8 - -- - b it o tp m cu b it o tp m cu b it o tp m cu b it o tp m cu v 1. 0 v 1. 0 v 1. 0 v 1. 0 ( (( ( 2010 2010 2010 2010- -- -4 44 4- -- -6 66 6) )) ) shanghai belling co., ltd.
tel86-21-64850700 web: www.belling.com.cn page 2 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. 1 11 1 general description general description general description general description BL35P02 is a single-chip 8-bit micro-controller. th is device integrates a hc05 8-bit cpu core, ram, rom, timer, programmable input/output pins and carr ier synthesizer. when in standby status, system wil l stop oscillator and remain low power consumption. the bl 35p02 is suitable for infrared remote control trans mitter application. 2 22 2 features features features features 8-bit cisc core compatible with motorola hc05 14 cmos bi-directional i/o pins and 1 cmos input pi n one 8-bit timer 9 keyboard interruption one infrared remote output, 8 kinds of carrier wave selected (1/3 duty crystal/ceramic oscillator(325k-8mhz) low powerstandby current less than 1ua@3v 32*8 bits ramincluding stack 2k*8 bits otp rom otp data encrypted operation voltage:2.0-5.5v packagesop20(300mil)/ssop20(200mil)/sop16(150mil) 3 33 3 pin pin pin pin configuration configuration configuration configuration sop20/ssop20 sop20 300mil sop16 150mil ssop20 200mil
tel86-21-64850700 web: www.belling.com.cn page 3 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. name in/out description osci input osco output the osci and osco pins are the connections for the on- chip oscillator gnd source ground vdd source power irout output infrared remote output vpp/pb0 input high voltage power supply as otp programming normal input , keyboard interrupt input port pb2-pb7 i/o bit- programmable i/o port for schmitt trigger input or push- pull output. pull- up resistors are assignable by software. pa0-pa7 i/o bit- programmable i/o port for schmitt trigger input or push- pull output. pull- up resistors are assignable by software. keyboard interrupt input port 4 44 4 block diagram block diagram block diagram block diagram
tel86-21-64850700 web: www.belling.com.cn page 4 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. 5 55 5 electrical characteristics electrical characteristics electrical characteristics electrical characteristics 5.1 5.15.1 5.1 absolute maximum ratings absolute maximum ratings absolute maximum ratings absolute maximum ratings parameter parameter parameter parameter symbol symbol symbol symbol value value value value unit unit unit unit operating voltage vdd -0.3~6.5 v input voltage vin vss-0.3 vdd+0.3 v operating ambient temperature ta -20 85 storage temerature tstg -65 150 5.2 5.25.2 5.2 dc electrical characteristics dc electrical characteristics dc electrical characteristics dc electrical characteristics vdd=3.0v vdd=3.0v vdd=3.0v vdd=3.0v gnd=0v, gnd=0v, gnd=0v, gnd=0v,t=25 t=25 t=25 t=25 , unless otherwise specified , unless otherwise specified , unless otherwise specified , unless otherwise specified parameter parameter parameter parameter symbol symbol symbol symbol pin pinpin pin c cc condition ondition ondition ondition min. min. min. min. typ. typ. typ. typ. m mm max. ax.ax. ax. u uu unit nitnit nit operating voltage vdd 2.0 3.0 5.5 v output high voltage driving current i oh pa7~pa0 pb7~pb2 irout v oh 2.7v 3 5 ma i ol1 pa7~pa0 pb7~pb2 v ol 0.3v 10 14 ma output low voltage sink current i ol2 irout v ol 0.3v 20 22 ma input high voltage v ih pa7~pa0 pb7~pb2 pb0 0.7vdd vdd v input low voltage v il pa7~pa0 pb7~pb2 pb0 0 0.2vdd v lvr voltage v lvr 0-40 1.15 1.40 1.65 v stop current i st vdd stop mode 0.1 1 ua pull-up resistor r p pa7~pa0 pb7~pb2 10 25 50 kohm 5.3 5.35.3 5.3 ac elect ac elect ac elect ac electrical characteristics rical characteristics rical characteristics rical characteristics vdd=3.0v vdd=3.0v vdd=3.0v vdd=3.0v gnd=0v, gnd=0v, gnd=0v, gnd=0v,t=25 t=25 t=25 t=25 parameter parameter parameter parameter symbol symbol symbol symbol min. min. min. min. typ. typ. typ. typ. max. max. max. max. u uu unit nitnit nit oscillator frequency f osc 325k 8m hz oscillator start time t oxov 20 ms
tel86-21-64850700 web: www.belling.com.cn page 5 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. 6 66 6 function description function description function description function description 6.1 6.16.1 6.1 instr instr instr instru uu uc cc ctions tions tions tions see section 7 for details on the instructions. 6.2 6.2 6.2 6.2 address spaces address spaces address spaces address spaces $0000-$000f control registers $0010-$00df reserved $00e0-$00ff ram $0100-$17ff reserved $1800-$1fff otp rom 6.3 6.3 6.3 6.3 crystal oscillator crystal oscillator crystal oscillator crystal oscillator 6.3 6.36.3 6.3.1 .1.1 .1 high frequency high frequency high frequency high frequency o oo oscillator scillator scillator scillator simplified external crystal/ceramic oscillator circ uits are shown in figure 6.3.1.1. an external cryst al or ceramic oscillation source provides 355khz~8mhz. th e load capacitor cx which values used in the oscill ator circuit design should include all stray capacitance is necessary, but frequency is more than 3.5mhz, c x can be removed. the crystal and components should be mount ed as close as possible to the pins for start-up stabilization and to minimize output distortion. frequency frequency frequency frequency value of value of value of value of cx cxcx cx 8mhz 0 /15p 4mhz 0 /15p/30p 3.64mhz 0 /15p/30p figure 6.3.1.1 6.3 6.36.3 6.3. .. .2 22 2 455khz 455khz 455khz 455khz oscillator oscillator oscillator oscillator using 455khz crystal/ceramic oscillation is shown f igure 6.3.2.1 generally osci/osco must be connected external 200pf capacitor. otherwise osco can be connected 2k to 5k resistor that can be used by carbon film resistor. figure 6.3.2.1 c x c x o sc illa to r o s c i o s c o
tel86-21-64850700 web: www.belling.com.cn page 6 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. 6.4 6.4 6.4 6.4 i/o ports i/o ports i/o ports i/o ports the mcu provides 14 bi-directional i/o pins (pa7-pa 0, pb7-pb2) and 1 input pin (pb0). the individual bits in these ports are programmable as either inpu ts or outputs under software control by the data di rection registers (ddrx). all port pins each has an associa ted 25k pull-up resistor, which can be connected/disconnected under software control. each port pin is controlled by the corresponding bits i n a data direction register and a data register as show n in figure 6.4.1, figure 6.4.1 the functions of the i/o pins are summarized as fol lows: read/write read/write read/write read/write ddr ddrddr ddrx xx x function function function function write 0 the i/o pins is in input mode. data is written into the output data latch write 1 data is written into the output data latch and outp ut to the i/o pin. read 0 the state of the i/o pin is read. read 1 the i/o pin is in an output mode. the output data latch is read. port a is configured for use as keyboard interrupts when the kbie bit is set in the miscellaneous cont rol register (mcr). individual keyboard interrupt port pins are also maskable by setting corresponding bit s in the keyboard interrupt mask register (kbim). when the k bex bit is set, the corresponding port a pin will t he configured as an input pin, regardless of the ddr s etting, and a 25k pull-up resistor is connected to the pin. see section 6.7.1 for details on the keyboard inter rupts. when port b is used input port, it has an associate d 25k pull-up resistor, which can be connected/disconnected under software control. as p ort b is used output port, it has not an associated 25 k pull-up resistor. pb2s pull-up resistor is control led by pbp2 of mcr, pb3s pull-up resistor is contr olled by pbp3 of mcr. pb4~pb7s pull-up resistors are contro lled by pbp of mcr. when otp is programming, pb0 is used high voltage i nput, normally it is used input port that has no pull-up resistor, and configured for use as a keybo ard interrupt when the kbeb0 is set in ddrb. see se ction 6.7.1 for details on the keyboard interrupts. 6.5 6.5 6.5 6.5 t tt timer imer imer imer the BL35P02 timer block diagram is shown in figure 6.5.1. the timer contains a single 8-bit software programmable count-down counter with a 7-bit softwa re selectable prescaler. the counter may be preset under software control and decrements towards zero. when the counter decrements to zero, the timer interrupt flag
tel86-21-64850700 web: www.belling.com.cn page 7 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. (tif bit in timer control register, tcr) is set. on ce timer interrupt flag is set, an interrupt is gen erated to the cpu only if the tim bit in the tcr and 1-bit in the ccr are cleared. when an interrupt is recognized, after completion of the current instruction, the processo r proceeds to store the appropriate registers on th e stack and then fetches the timer interrupt vector from locati ons $1ff6 and $1ff7. see section 6.7.2 for details on the timer interrupts. the counter may be read at any time by the processo r without disturbing the count. the contents of the counter become stable prior to the read portion of a cycle and do not change during the read. the time r interrupt flag remains set until cleared by the software. if a write occurs before the timer interrupt is served , the interrupt is lost. the timer interrupt flag may also be sued as a scanned status bit in a non-interrupt mode of operation. the prescaler is a 7-bit divider which is used to e xtend the maximum length of the timer. bit 0,1,2(pr0,pr1,pr2) of tcr are programmed to choose the appropriate prescaler output which is used as t he 8-bit counter clock input. the processor cannot wri te into or read from the prescaler; however, its co ntents can be cleared to all zeros by writing to the prer bit in the tcr. this will allow for truncation-free cou nting. tif tim prer pr2 pr1 pr0 tcr tdr prescaler prescaler select logic prescaler reset overflow interrupt control ck system clock 8 dbus 8 8 figure 6.5.1 6.6 6.6 6.6 6.6 remote control carrier synthesizer remote control carrier synthesizer remote control carrier synthesizer remote control carrier synthesizer the device has a built carrier synthesizer for infr ared or rf remote control circuits. the carriers d uty is 1/3. the carrier synthesizer can be programmed in s everal different prescaler ratios by setting fc[2:0 ] of otps option bit. irout of the remote control carrier syn thesizer output is shown in figure 6.6.1.
tel86-21-64850700 web: www.belling.com.cn page 8 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. figure 6.6.1 fcae and outc of mcr are programmed to control the carrier has remote code or not. either fcae or outc is clear, the carrier prescaler will be reset to make the first remote code with the carrier full . the waves of irout, fcae and outc are shown as follows: the carrier of irout is based on the system clock t hat is half of oscillator frequency. it is programm ed in eight different prescaler ratios by setting fc[2:0] of otps option that is shown as follows: fc fcfc fc[2:0] [2:0] [2:0] [2:0] prescaler di prescaler di prescaler di prescaler divide ratio vide ratio vide ratio vide ratio o oo of f f f s ss system ystem ystem ystem c cc cl ll lo oo ock ckck ck o oo oscillator scillator scillator scillator f ff frequency requency requency requency t tt the carrier frequency he carrier frequency he carrier frequency he carrier frequency of of of of irout irout irout irout 000 6 445khz 37.91k 001 36 4mhz 55.56k 010 50 4mhz 40.00k 011 53 4mhz 37.74k 100 56 4mhz 35.71k 101 61 4mhz 32.78k 110 64 4mhz 31.25k 111 74 4mhz 27.03k 6.7 6.7 6.7 6.7 i ii inte ntente nterrup rrup rrup rrupt tt ts ss s the BL35P02 mcu can be interrupted by different sou rces including two maskable hardware interrupts keyboard interrupt (kbi) and timer overflow interru pt (tmi) and one non-maskable software interrupt software interrupt(swi). if the interrupt mask bit (i-bit) in the condition code register (ccr) is set , all maskable interrupts are disabled. clearing the i-bi t enables interrupts. the software interrupt (swi) is an executable instruction and a non-maskable interrupt : it is execute regardless of the state of the i-bi t in the ccr. if the i-bit is zero (interrupt enabled), swi is ex ecuted after interrupts that were pending when the swi was fetched, but before interrupts generated after the swi was fetched. the swi interrupt service routine address is specified by the contents of locations $1ffc and $1 ffd
tel86-21-64850700 web: www.belling.com.cn page 9 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. 6.7.1 6.7.1 6.7.1 6.7.1 keyboard interrupt (kbi) keyboard interrupt (kbi) keyboard interrupt (kbi) keyboard interrupt (kbi) keyboard interrupt function is associated with port a pins and pb0 pin. the keyboard interrupt functio n is enabled by setting the keyboard interrupt enable bi t kbie (bit 7 of mcr at $0c) and the individual ena ble bits kbe0-kbe7 (bits 0-7 kbim at $0b) and kbeb0 (bit 0 o f ddrb). when the kbex bit is set, the corresponding port a pin will be configure as an in put pin, regardless of the ddr setting, and a 25k pull-up resistor is connected to the pin, as shown in figur e 6.7.1.1. when a high to low transition is sensed on the pin, a keyboard interrupt will be generated. an interrupt to the cpu will be generated if the i-bi in the ccr is cleared. the keyboard interrupt flag should be cleared in th e interrupt service routine (by writing a 1 to kb ic bit in the mcr at $0c) after the key is debounced. debo ncing will avoid spurious false triggering. the keyboard interrupt is negative-edge sensitive o nly, and the interrupt service routine is specified by the contents in $1ff4-$1ff5. figure 6.7.1.1 6.7.2 6.7.2 6.7.2 6.7.2 t tt timer interrupt imer interrupt imer interrupt imer interrupt the timer interrupt is generated by the 8-bit timer when a timer overflow has occurred. the interrupt enable and flag for the timer interrupt are located in the timer control register (tcr). (1) timer interrupt mask (tim). when tim is equal t o 1, timer interrupt is disabled. when tim is equal to 0, timer interrupt is enabled. (2) timer interrupt flag (tif). when tif is equal t o 1, a timer interrupt (timer overflow) has occur red. when tif is equal to 0, a timer interrupt (timer overflow) has not occurred. the i-bit in the ccr must be cleared in order for t he timer interrupt to be processed. the interrupt w ill vector to the interrupt service routine at the addr ess specified by the contents in $1ff6-$1ff7. 6.7.3 6.7.3 6.7.3 6.7.3 i ii interrupts process nterrupts process nterrupts process nterrupts process interrupts cause the processor to save the register contents on the stack and to set the interrupt mas k (i-bit) to prevent additional interrupts. the rti instructi on causes the register contents to be recovered fro m the stack and normal processing to resume. unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. the current instruction is the on alread y fetched and being operated on. when the current instruction is complete, the processor checks all pending hard ware interrupts. if interrupts are not masked (ccr i-bit clear) the processor proceeds with interrupt proce ssing; otherwise, the next instruction is fetched and exec uted. the relative priority of all the possible sou rces is shown
tel86-21-64850700 web: www.belling.com.cn page 10 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. as follows: interrupt interrupt interrupt interrupt v vv vector address ector address ector address ector address prio prio prio priori riri rity tyty ty kbi $1ff4:$1ff5 tmi $1ff6:$1ff7 swi $1ffc:$1ffd reset $1ffe:$1fff lowest highest 6.8 6.8 6.8 6.8 low power modes low power modes low power modes low power modes the BL35P02 has two low-power modes. the wait and s top instructions provide two modes that reduce the power required for the mcu by stopping various internal clocks and/or the on-chip oscillator. 6.8.1 6.8.1 6.8.1 6.8.1 s s s stop toptop top mode mode mode mode execution of the stop instruction places the mcu in its power consumption mode. in the stop mode the internal oscillator is turned off, halting all inte rnal processing. when the cpu enters stop mode the i-bit in the ccr is cleared automatically, all other registers and memory contents remain unaltered. all input/output lines remain unchanged. the mcu can be brought out of the stop mode only by a kbi interrupt or an externally generated reset. when exiting the stop mode the internal oscillator will resume after a pre-defined number of internal processor clock cycles, due to oscillator stabiliza tion. in stop mode the current of BL35P02 is less than 1u a. 6.8.2 wait 6.8.2 wait 6.8.2 wait 6.8.2 wait mode mode mode mode the wait instruction places the mcu in a low-power mode, but consumes more power than the stop mode, in the wait mode the internal processor clock is halted, suspending all processor and internal b us activities. other internal clocks remain active, pe rmitting interrupts to be generated from the timer. the timer may be used to generate a periodic exit from the wa it mode or in conjunction with the external timer p in, on the occurrence of external events. execution of the wait instruction automatically clears the i-bit in the ccr, so that the kbi interrupt, timer interrupt or exter nally generated reset can wake the mcu. all other registers, memory, and input/output lines remain in their prev ious states. in wait mode the current of BL35P02 is less than 10 0ua @3v. 6.9 6.9 6.9 6.9 control register control register control register control registers summary s summary s summary s summary a summary of all control registers is shown as foll ows: register name address r/w state on reset pa $00 r/w 0000 0000 pb $01 r/w 0000 00-0 ddra $04 r/w 0000 0000 ddrb $05 r/w 0000 00-0 tdr $08 r/w uuuu uuuu tcr $09 r/w 01-- 0100 kbim $0b r/w 0000 0000
tel86-21-64850700 web: www.belling.com.cn page 11 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. mcr $0c r/w 00-0 0000 notice -: is undefined u: is unaffected. pa papa pa ($00): p ($00): p ($00): p ($00): port a data register ort a data register ort a data register ort a data registers ss s .7-.0 pa[7:0] when a port a pin is programmed as an output the st ate of the corresponding data register bit determines the state of the output pin. when a port a pin is programmed as an input, a read of the port a data register will return the logic state of the corresponding port a pin. ddra($0 ddra($0 ddra($0 ddra($04 44 4): port a data direction registers ): port a data direction registers ): port a data direction registers ): port a data direction registers .7-.0 ddra[7:0] port a pin may be programmed as an input or output by clearing or setting the corresponding bit int ddra. 0 (clear) - port a pin is used as an input 1 (set) - port a pin is used as output pb ($02): p pb ($02): p pb ($02): p pb ($02): port b data registers ort b data registers ort b data registers ort b data registers .7-.2,.0 pb[7:2,0] when a port b pin is programmed as an output the st ate of the corresponding data register bit determines the state of the output pin. when a port b pin is programmed as an input, a read of the port b data register will return the logic state of the corresponding port b pin. ddrb($0 ddrb($0 ddrb($0 ddrb($05 55 5): ): ): ): port b data direction registers port b data direction registers port b data direction registers port b data direction registers .7-.2 ddrb[7:2] port b pin may be programmed as an input or output by clearing or setting the corresponding bit int ddra. 0 (clear) - port a pin is used as an input 1 (set) - port a pin is used as output .0 kbeb0 C pb0 keyboard interrupt enable kbeb0 is a keyboard interrupt enable bit of pb0 pin 0 (clear) C keyboard interrupt of pb0 pin disabl ed. 1 (set) - keyboard interrupt of pb0 pi n enabled. pb0 has no pull-up resistor. tdr($08): tdr($08): tdr($08): tdr($08): timer data register timer data register timer data register timer data register the tdr is a read/write register which contains the current value of the 8-bit count-down timer counter when read. reading this register does not d isturb the counter operation. tcr($09): tcr($09): tcr($09): tcr($09): timer control register timer control register timer control register timer control register .7 tif C timer interrupt flag 0 (clear) C the timer has not reached a count of ze ro. 1 (set) - the timer has reached a count of zero. the timer interrupt flag is set when the 8-bit coun ter decrements to zero. this bit is cleared on reset, or by writing a 0 to the tif bit. .6 tim C timer interrupt mask 0 (clear) C timer interrupt request to the cpu is n ot masked (enable). 1 (set) C timer interrupt request to the cup is mas ked (disable).
tel86-21-64850700 web: www.belling.com.cn page 12 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. a reset sets this bit to one; it must then be clear ed by software to enable the timer interrupt to the cpu. this timer interrupt ma sk only masks timer interrupt request to the cpu, and does not affect counting of the 8-b it counter or the setting of tif. .3 prer C prescaler reset writing a 1 to this write-only bit will reset the prescaler to zero, which is necessary for any new counts set by writing to t he timer data register. this bit always reads as zero, and is not affected by reset. .2-.0 pr[2:0] these three bits enable the program to select the d ivision ratio of the prescaler. on reset, these three bits are set to 100, which corresponds to a division ratio of 16. pr2 pr2pr2 pr2 pr1 pr1pr1 pr1 pr0 pr0pr0 pr0 d dd divide ration ivide ration ivide ration ivide ration 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 kbim($0b): kbim($0b): kbim($0b): kbim($0b): keyboard interrupt mask register keyboard interrupt mask register keyboard interrupt mask register keyboard interrupt mask register .7-.0 kbe [ 7:0] the keyboard interrupt mask register (kbim) masks i ndividual keyboard interrupt pins and setting of the internal pull-up resistors on port a . kbei C pai keyboard interrupt enable 0 (clear) C keyboard interrupt for pai pin is maske d. any transitions on pai will not set any flags. 1 (set) C keyboard interrupt enabled for pai. a 25k internal pull-up resistor is connected. high to low transition on pai will cause a keyboard interrupt. mcr($0c): mcr($0c): mcr($0c): mcr($0c): miscellaneous control register miscellaneous control register miscellaneous control register miscellaneous control register .7 kbie C keyboard interrupt enable 0 (clear) - keyboard interrupts master disabled. 1 (set ) C keyboard interrupts master enabled. on reset, kbie bit is clear to 0. kbie and kbei c ontrol the master enable for the keyboard interrupts. .6 kbic C keyboard interrupt clear 0 (clear) C writing a 0 has no effect. 1 (set) C writing a 1 clears the keyboard interru pt latch. on reset, kbic bit is clear to 0. this is a write -only bit and always read as 0. .5 reserved .4 pbp C pb7:pb4 pull-up 0 (clear) C no pull-up resistor is connected to the inputs of pb7-pb4. 1 (set) C the internal 25k pull-up resistors are connected to the inputs of p b7-pb4 .3 pbp3 C pb3 pull-up
tel86-21-64850700 web: www.belling.com.cn page 13 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. 0 (clear) C no pull-up resistor is connected to the inputs of pb3. 1 (set) C the internal 25k pull-up resistor is connected to the inputs of pb3 .2 pbp2 C pb2 pull-up 0 (clear) C no pull-up resistor is connected to the inputs of pb2. 1 (set) C the internal 25k pull-up resistor is connected to the inputs of pb2 .1 outc 0 (clear) C irout output logic 0 1 (clear) C irout output logic 1 .0 fcae 0 (clear) - irout output without carrier 1 (set) C irout output with carrier 6.10 option bit 6.10 option bit 6.10 option bit 6.10 option bit option bit (opbit) is a special byte in otp rom and used to config some initial functions for the device. opbit is set when otp is programming. .7 encr 0: otp read protection 1: otp can be read .6-.3 reserved .2-.0 fc[2:0] fc[2:0] carrier divide ratio carrier frequency @ oscillator frequency 000 fsys/6 38khz@455khz osc 001 fsys/36 56khz@4mhz osc 010 fsys/50 40khz@4mhz osc 011 fsys/53 38khz@4mhz osc 100 fsys/56 36khz@4mhz osc 101 fsys/61 33khz@4mhz osc 110 fsys/64 31.5khz@4mhz osc 111 fsys/74 27khz@4mhz osc
tel86-21-64850700 web: www.belling.com.cn page 14 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. 7. instruction set 7.1 addressing modes the addressing modes define the manner in which an instruction is to obtain the data required for its execution. there are 8 modes: 1) inherent 2) immediate 3) direct 4) extended 5) indexed, no offset 6) indexed, 8-bit offset 7) indexed, 16-bit offset 8) relative 7.1.1 inherent addressing mode in inherent addressing mode, all information requir ed for the operation is already inherently known to the cpu, and no external operand from memory or fro m the program is needed. the operands, if any, are only the index register and accumulator, and ar e always 1-byte instructions. 7.1.2 immediate addressing mode in the immediate addressing mode, the operand is co ntained in the byte immediately following the opcode. this mode is used to hold a value or consta nt which is known at the time the program is written and which is not changed during program exe cution. these are 2-byte instructions, one for the opcode and one for the immediate data byte. 7.1.3 direct addressing mode the direct addressing mode is similar to the extend ed addressing mode except the upper byte of the operand address is assumed to be $00. thus, only th e lower byte of the operand address needs to be included in the instruction. direct addressing allo ws you to efficiently address the lowest 256 bytes in memory. this area of memory is called the direct pa ge and includes on-chip ram and i/o registers. direct addressing is efficient in both memory and t ime. direct addressing mode instructions are usuall y two bytes, one for the opcode and one for the low-o rder byte of the operand address. 7.1.4 extended addressing mode in the extended addressing mode, the address of the operand is contained in the two bytes following the opcode. extended addressing references any loca tion in the mcu memory space including i/o, ram, rom and eprom. extended addressing mode instru ctions are three bytes, one for the opcode and two for the address of the operand. 7.1.5 indexed, no offset addressing mode in the indexed, no-offset addressing mode, the effe ctive address of the instruction is contained in th e 8-bit index register. thus, this addressing mode ca n access the first 256 memory locations. these instructions are only one byte. 7.1.6 indexed, 8-bit offset addressing mode
tel86-21-64850700 web: www.belling.com.cn page 15 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. in the indexed, 8-bit offset addressing mode, the e ffective address is obtained by adding the contents of the byte following the opcode to the contents of the index register. this mode of addressing is use ful for selecting the kth element in an n element table . to use this mode, the table must begin in the lowest 256 memory locations and may extend through the first 511 memory locations (ife is the last location which the instruction may access). indexed 8-bit offset addressing can be used for rom, ram, or i/o. this is a 2-byte instruction with the offset contained in the byte following the opcode. the content of the index register (x) is not changed. t he offset byte supplied in the instruction is an unsigned 8-bit integer. 7.1.7 indexed, 16-bit offset addressing mode in the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the 8-bit index register and the two bytes following th e opcode. the content of the index register is not changed. these instructions are three bytes, one fo r the opcode and two for a 16-bit offset. 7.1.8 relative addressing mode the relative addressing mode is used only for branc h instructions. branch instructions, other than the branching versions of bit-manipulation instructions , generate two machine-code bytes: one for the opcode and one for the relative offset. because it is desirable to branch in either direction, the off set byte is a signed twos-complement offset with a rang e of C127 to +128 bytes (with respect to the address of the instruction immediately following th e branch instruction). if the branch condition is t rue, the contents of the 8-bit signed byte following the opcode (offset) are added to the contents of the program counter to form the effective branch addres s; otherwise, control proceeds to the instruction immediately following the branch instruction. 7.2 instruction type there are 65 instructions in cpu, and can be divide d into 5 types. 1) register/memory instructions 2) read/modify-write instructions 3) branch instructions 4) control instructions 5) bit manipulate instructions
tel86-21-64850700 web: www.belling.com.cn page 16 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. 7.3 instruction set status instructions operating function h i n z c address ing modes opcode opdata #cycle adc #opr adc opr adc opr adc opr,x adc opr,x adc ,x add with carry a (a)+(m)+(c) * - * * * imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add #opr add opr add opr add opr,x add opr,x add ,x add without carry a (a)+(m) * - * * * imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and #opr and opr and opr and opr,x and opr,x and ,x logical and a (a) (m) - - * * - imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr,x asl ,x arithmetic shift left (same as lsl) c 0 b7 b0 - - * * * dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr,x asr ,x arithmetic shift right c b7 b0 - - * * * dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc (pc)+2+rel ? c=0 - - - - - rel 24 rr 3
tel86-21-64850700 web: www.belling.com.cn page 17 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bclr n opr clear bit n mn 0 - - - - - dir(bo) dir(b1) dir(b2) dir(b3) dir(b4) dir(b5) dir(b6) dir(b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc (pc)+2+rel ? c=1 the same as blo - - - - - rel 25 rr 3 beq rel branch if equal pc (pc)+2+rel ? z=1 - - - - - rel 27 rr 3 bhcc rel branch if half carry bit clear pc (pc)+2+rel ? h=0 - - - - - rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc)+2+rel ? h=1 - - - - - rel 29 rr 3 bhi rel branch if higher pc (pc)+2+rel ? (c z )=0 - - - - - rel 22 rr 3 bhs rel branch if higher or same pc (pc)+2+rel ? c=0 - - - - - rel 24 rr 3 bit #opr bit opr bit opr bit opr,x bit opr,x bit ,x bit test accumulator with memory byte (a) (m) - - * * - imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc (pc)+2+rel ? c=1 - - - - - rel 25 rr 3 bls rel branch if lower or same pc (pc)+2+rel ? (c z )=1 - - - - - rel 23 rr 3 bmc rel branch if interrupt mask clear pc (pc)+2+rel ? i=0 - - - - - rel 2c rr 3 bmi rel branch if minus pc (pc)+2+rel ? n=1 - - - - - rel 2b rr 3
tel86-21-64850700 web: www.belling.com.cn page 18 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. bms rel branch if interrupt mask set pc (pc)+2+rel ? i=1 - - - - - rel 2d rr 3 bne rel branch if not equal pc (pc)+2+rel ? z=0 - - - - - rel 26 rr 3 bpl rel branch if plus pc (pc)+2+rel ? n=0 - - - - - rel 2a rr 3 bra rel branch always pc (pc)+2+rel - - - - - rel 20 rr 3 brclr n opr rel branch if bit n clear pc (pc)+2+rel ? mn=0 - - - - * dir(bo) dir(b1) dir(b2) dir(b3) dir(b4) dir(b5) dir(b6) dir(b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc)+2 - - - - - rel 21 rr 3 brset n opr rel branch if bit n set pc (pc)+2+rel ? mn=1 - - - - * dir(bo) dir(b1) dir(b2) dir(b3) dir(b4) dir(b5) dir(b6) dir(b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5
tel86-21-64850700 web: www.belling.com.cn page 19 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. dd rr dd rr bset n opr set bit n mn 1 - - - - - dir(bo) dir(b1) dir(b2) dir(b3) dir(b4) dir(b5) dir(b6) dir(b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc (pc)+2 push(pcl);sp (sp)- 1 push(pch);sp (sp)- 1 pc (pc)+rel - - - - - rel ad rr 6 clc clear carry bit c 0 - - - - 0 inh 98 2 cli clear interrupt mask i 0 - 0 - - - inh 9a 2 clr opr clra clrx clr opr,x clr ,x clear byte m $00 a $00 x $00 m $00 m $00 - - 0 1 - dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp #opr cmp opr cmp opr cmp opr,x cmp opr,x cmp ,x compare accumulator with memory byte (a) -(m) - - * * * imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr,x com ,x complement byte (ones complement) m $ff-(m) a $ff-(a) x $ff-(x) m $ff-(m) m $ff-(m) - - * * 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5
tel86-21-64850700 web: www.belling.com.cn page 20 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. cpx #opr cpx opr cpx opr cpx opr,x cpx opr,x cpx ,x compare index register with memory byte (x) -(m) - - * * * imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr,x dec ,x decrement byte m (m)-1 a (a)-1 x (x)-1 m (m)-1 m (m)-1 - - * * - dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor #opr eor opr eor opr eor opr,x eor opr,x eor ,x exclusive or accumulator with memory byte a (a) ? (m) - - * * - imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 inc opr inca incx inc opr,x inc ,x increment byte m (m)+1 a (a)+1 x (x)+1 m (m)+1 m (m)+1 - - * * - dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr,x jmp opr,x jmp ,x unconditional jump pc jump address - - - - - dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr,x jsr opr,x jsr ,x jump to subroutine pc (pc)+n(n=1,2,or 3) push (pcl);sp (sp)-1 push(pch);sp (sp)- 1 pc effective - - - - - dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5
tel86-21-64850700 web: www.belling.com.cn page 21 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. address lda #opr lda opr lda opr lda opr,x lda opr,x lda ,x load accumulator with memory byte a (m) - - * * - imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx #opr ldx opr ldx opr ldx opr,x ldx opr,x ldx ,x load index register with memory byte x (m) - - * * - imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr,x lsl ,x logical shift left (same as asl) c 0 b7 b0 - - * * * dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr,x lsr ,x logical shift right c 0 b7 b0 - - 0 * * dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x:a ? (x)x(a) 0 - - - 0 inh 42 1 1 neg opr nega negx neg opr,x neg ,x negate byte (twos complement) m -(m) a -(a) x -(x) m -(m) m -(m) - - * * * dir inh inh ix1 ix 30 40 50 60 70 dd ff 5 3 3 6 5 nop no operation - - - - - inh 9d 2 ora #opr ora opr ora opr ora opr,x logical or accumulator with memory a (a) (m) - - * * - imm dir ext ix2 aa ba ca da ii dd hh ll 2 3 4 5
tel86-21-64850700 web: www.belling.com.cn page 22 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. ora opr,x ora ,x ix1 ix ea fa ee ff ff 4 3 rol opr rola rolx rol opr,x rol ,x rotate byte left through carry bit c b7 b0 - - * * * dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 ror opr rora rorx ror opr,x ror ,x rotate byte right through carry bit c b7 b0 - - * * * dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp $00ff - - - - - inh 9c 2 rti return from interrupt sp (sp)+1; pull(ccr) sp (sp)+1; pull(a) sp (sp)+1; pull(x) sp (sp)+1; pull(pch) sp (sp)+1; pull(pcl) * * * * * inh 80 9 rts return from subroutine sp (sp)+1; pull(pch) sp (sp)+1; pull(pcl) - - - - - inh 81 6 sbc #opr sbc opr sbc opr sbc opr,x sbc opr,x sbc ,x subtract memory byte and carry bit from accumulator a (a)-(m)-(c) - - * * * imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c 1 - - - - 1 inh 99 2 sei set interrupt mask i 1 - 1 - - - inh 9b 2 sta opr sta opr store accumulator in dir ext b7 c7 dd hh 4 5
tel86-21-64850700 web: www.belling.com.cn page 23 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. sta opr,x sta opr,x sta ,x memory m (a) - - * * - ix2 ix1 ix d7 e7 f7 ll ee ff ff 6 5 4 stop stop oscillator and enable irq pin - 0 - - - inh 8e 2 stx opr stx opr stx opr,x stx opr,x stx ,x store index register in memory m (x) - - * * - dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 suc #opr sub opr sub opr sub opr,x sub opr,x sub ,x subtract memory byte from accumulator a (a)- (m) - - * * * imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc (pc)+1;push(pc l) sp (sp)-1;push(pc h) sp (sp)-1; push(x) sp (sp)-1; ush(ccr) sp (sp)-1;i 1 pch interrupt vector high byte pcl interrupt vector low byte - 1 - - - inh 83 10 tax transfer accumulator to index register x (a) - - - - - inh 97 2 tst opr tsta tstx tst opr,x test memory byte for negative or zero (m)-$00 - - * * - dir inh inh ix1 3d 4d 5d 6d dd ff 4 3 3 5
tel86-21-64850700 web: www.belling.com.cn page 24 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. tst ,x ix 7d 4 txa transfer index register to accumulator a (x) - - - - - inh 9f 2 wait stop cpu clock and enable interrupts - 0 - - - inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow flag pc program counter ccr condition code register pch program counter high byt e dd direct address of operand pcl program counter low byt e dd rr direct address of operand and relative offset of branch instruction rel relative addres sing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-b it offset addressing rr relative progra m counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry flag z zero flag hh ll high and low bytes of operand address in exte nded addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode ? logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode C( ) negation (twos compl ement) ix1 indexed, 8-bit offset addressing mode ? loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative flag ? set or cleared n any bit not affected not affected
tel86-21-64850700 web: www.belling.com.cn page 25 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. 8 88 8 package package package package sop20 300mil dimensions in mil dimensions in mil dimensions in mil dimensions in mil dimensions in milimeter dimensions in milimeter dimensions in milimeter dimensions in milimeter symbol symbol symbol symbol max. max. max. max. nom. nom. nom. nom. min. min. min. min. max. max. max. max. nom. nom. nom. nom. min. min. min. min. a 394 - 420 10.01 - 10.67 b 290 - 300 7.37 - 7.62 c 14 - 20 0.36 - 0.51 c' 495 - 512 12.57 - 13.00 d 92 - 104 2.34 - 2.64 e - 50 - - 1.27 - f 4 - - 0.10 - - g 32 - 38 0.81 - 0.97 h 4 - 12 0.10 - 0.30 0 - 8 0 - 8
tel86-21-64850700 web: www.belling.com.cn page 26 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. ssop20 200mil dimensions in mil dimensions in mil dimensions in mil dimensions in mil dimensions in milimeter dimensions in milimeter dimensions in milimeter dimensions in milimeter symbol symbol symbol symbol max. max. max. max. nom. nom. nom. nom. min. min. min. min. max. max. max. max. nom. nom. nom. nom. min. min. min. min. a 299 307 315 7.60 7.80 8.00 b 201 209 217 5.10 5.30 5.50 c 11 - 15 0.29 - 0.37 c' 276 283 291 7.00 7.20 7.40 d 51 59 67 1.30 1.50 1.70 e - 25.6 - - 0.65 - f 2 6 10 0.05 0.15 0.25 g 30 35 40 0.75 0.90 1.05 h 6 - 8 0.15 - 0.20 0 - 8 0 - 8
tel86-21-64850700 web: www.belling.com.cn page 27 of 27 BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet BL35P02 datasheet ?? ?? ?? ?? ?? ?? ?? ?? shanghai belling co., ltd. sop16 150mil dimensions in mil dimensions in mil dimensions in mil dimensions in mil dimensions in milimeter dimensions in milimeter dimensions in milimeter dimensions in milimeter symbol symbol symbol symbol max. max. max. max. nom. nom. nom. nom. min. min. min. min. max. max. max. max. nom. nom. nom. nom. min. min. min. min. a 238 - 244 6.05 - 6.20 b 150 - 157 3.80 - 4.00 c 14 - 19 0.36 - 0.48 c' 386 - 398 9.80 - 10.10 d 53 - 62 1.35 - 1.57 e - 50 - - 1.27 - f 4 - - 0.10 - - g 22 - 32 0.56 - 0.82 h 4 - 12 0.10 - 0.30 0 - 8 0 - 8

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